Capacitive read only memory

ABSTRACT

A capacitive read only memory operable to respond to the logical product of the inputs to the memory. The read only memory consists of a pair of plates or memory planes capacitively coupled together. Circuitry logically inverts the input pulses to the first plane and selective capacitor placement creates pulsing on all outputs from the second plane except on the desired output. Circuitry logically inverts the pulses from the second plane resulting in an output which is the logical product of the input signals.

United States Patent [191 Eldert [451 Feb. 5, 1974 [541 CAPACITIVE READONLY MEMORY 3,681,761 8/1972 Schuenemann 340/1725 I 3,350,691 l/l967Faulis 340/173 CA [75] lnvemormenus Elder" 3,678,473 7/1972 Wahlstrom .1340/173 CA 73 Assignee; Burroughs Comm-anon, Detroit, 3,701,120 10/1972Charters 340/ 173 CA Mich. Primary Examiner-Paul J. Henon [22] June 1972Assistant Examiner-John P. Vandenburg 21] AppL 265 9 3 Attorney, Agent,or FirmRalzemond B. Parker; Ed-

win W. Uren; Edward G. Fiorito [52] US. Cl. 340/172.5, 340/173 SP,30,35,191: [57] ABSTRACT 51 1 Int. Cl G1 1c 17/00 A capacitive readmemory Operable respond [58] Field of Search 340/1725 173 CA 173 R thelogical product of the inputs to the memory. The

340/173 SP 174 307/218: 328/94 read only memory consists of a pair ofplates or memory planes capacitively coupled together. Circuitrylogically inverts the input pulses to the first plane and [56]References Cited selective capacitor placement creates pulsing on alloutputs from the second plane except on the desired UNITED STATESPATENTS output. Circuitry logically inverts the pulses from the 5 secondplane resulting in an output which is the logiarman 1 1 1. 3,593,3047/l97l Gardner 34O/l7215 cal product of the Input slgnals 3,593,3177/1971 Fleisher 340/1725 7 Claims, 4 Drawing Figures 36 40 7 54 2 54 42A W2 F l l j i 56 1 w f 42 c C D C D C D 0 Q Q BACKGROUND OF THEINVENTION 1. Field of the Invention This invention provides circuitmeans for generating the logical product in a composable capacitive readonly memory. The semiconductor composable read only memory in thepresent state of the art is a large micro-logic array of semiconductorcells fabricated on a single silicon chip using MOS technology. Onesignificant use of the composable capacitive read only memory or CCROM,is in developing prototypes of computer oriented products and fordebugging new products. These CCROMs are field alterable, that is,various logic connections may be changed on location during developmentdebugging. It is therefore unnecessary to require a new memory to befabricated each time an error is detected in the logic or each time adifferent logic sequence is to be evaluated.

2. Description of the Prior Art The read only memory, or ROM, has beenused for several years in semiconductor and capacitive forms. However,capacitive read only memories operate to provide the logical OR, or sumfunction. Prior to the present invention it was not known how to operatethe capacitive read only memory to provide the logical AND or productfunction.

SUMMARY OF THE INVENTION In view of the inability of the prior arttechniques to provide a capacitive read only memory operable to generatethe logical product of the input signals, it is an object of the presentinvention to provide a composable capacitive read only memory operablein such a fashion.

It is a further object of the present invention to provide a capacitiveread only memory which may be cascaded with other memories to providevarious logical functions such as AND-OR, AND-AND, OROR, OR- AND andsimilar combinations of three or more memones.

These and other objects and advantages of the present invention areaccomplished in a capacitive read only memory including input gatingmeans to logically invert the input pulses, pulsing all output lines ofthe CROM except the desired line, and output logical inverting means forproviding an output only for the nonpulsing line.

DESCRIPTION OF THE DRAWINGS The foregoing objects and advantages of thepresent invention, together with other advantages which may be attainedby its use, will be apparent upon reading the following detaileddescription taken in conjunction with the drawings. In the drawingswherein like numerals identify corresponding parts:

FIG. 1 illustrates a prior art semiconductor product ROM;

FIG. 2 illustrates a prior art sum CROM;Y

FIG. 3 indicates a CROM operable to provide the logical productaccording to the principles of the present invention; and

FIG. 4 illustrates the. technique for cascading two CROMs together.

DESCRIPTION OF THE PREFERRED EMBODIMENT In order to set the presentinvention in its proper perspective, a brief description of the priorart read only memories will be beneficial. With reference first to FIG.I there is illustrated a prior art ROM 10 connected to provide thelogical product or AND function. The ROM 10 contains a plurality ofinput lines 12A, 12B and a plurality of output lines 14A, 148. Each*true" input line 12A, 12B branches through an inverter 16A, 16B,respectively to a corresponding complement input line 18A, 188. Selectedtrue and complement lines are connected via MOS transistors to theappropriate output lines 14A, 14B depending upon the logic desired fromthe read only memory. In the illustration of FIG. 1, if it is desired toform the logical product A B, the input line 12A which reflects thesignal A is connected via a MOS transistor 20A to sense line or outputline MA. This connection is made by coupling the gate of the MOS toinput line 12A, the source electrode to a voltage V and the drainelectrode through a resistor 22A to a source of negative potential (or,alternatively, to ground).

The complement of the signal B, which appears on line 183, is connectedvia M05 208 to the output line 14A.

The operation of the circuit is as follows: If line 12A is active andline 128 is inactive, MOS 20A and 20B are both Off and output 24A is atV. Otherwise, output 24A is at V; potential. Thus the product A B issensed.

Having thus explained the operation of the prior art product" ROM, theoperation of the prior art capacitive ROM, which operated only in thelogical OR mode prior to the present invention will be explained. Withreference to FIG. 2 the capacitive ROM, or CROM 26 includes a pluralityof input or word lines W,, W W W, in a first plane and a plurality ofsense or output lines 8,, S S 5,, in a second plane. Various word linesand sense lines are capacitively coupled 28 depending upon the arbitrarylogic which the memory is designed to perform. In the presentillustration if it is desired to activate sense line S, upon the pulsingof W, or W, then the intersection of W, and S, is capacitively coupledand intersection of W, and S, is capacitively coupled. A signal on W, orW, or both, through the capacitive coupling, generates an output pulseon line S A table is included as part of FIG. 2 to show the vari ouslogical conditions preselected with the CROM 26 of FIG. 2.

Thus it may be seen that in the prior art CROM only the logicalsummation or OR mode was attainable prior to the invention describedherein, where the logical product or AND mode was desired it wasnecessary to utilize a non-capacitive memory.

With reference now to FIG. 3, there is illustrated a capacitive readonly memory or CROM including the inversion circuitry according to theprinciples of the present invention to permit the CROM to operate in theproduct mode. The CROM of FIG. 3 includes a plurality of input or wordlines W,, W,. W, in a first plane and a plurality of sense or outputlines 8,, 8,. S, in a second plane. Each input line drives the CROM inboth true and complement form. One branch of the input line W, is passedthrough an inverter 30 and the output thereof is one input to a twoinput AND gate 32.

This is the complement signal for the input pulse because of theinverter 30. The true input on line 34 is one input to a two input ANDgate 36. The second input to each AND gate 32, 36 is a clock pulse attime T,. The output of the first AND gate 32 appears on line 38 and theoutput of the second AND gate 36 appears on line 40. There is similarlogic circuitry for each input line or word line, however it will onlybe explained for word line W,. Selected word lines are capacitivelycoupled 42 to predetermined sense lines based on the arbitrary logicwhich the CROM is intended to perform.

Each sense line 8,. S,, is connected as one input to a two inputinverting gating comparator 44 which performs several functions. Theother input to this comparator 44 is a threshold voltage V Thecomparator 44 compares the threshold voltage to the voltage appearing onthe sense line and, if the sense line voltage exceeds the thresholdvoltage, the comparator is gated or enabled. At the same time the outputis inverted resulting in a low signal. If the voltage on the sense lineis lower than the threshold voltage, the output of the comparator 44 ishigh or one."

The output of each comparator 44 serves as one input, the D or datainput to a D type flip flop 46. The clock pulse or C input to each Dflip flop 46 is applied at time T The output of each D type flip flopappears at the terminal 48.

Having thus explained the structure of the CROM according to the presentinvention, the operation under various conditions will now be explained.It should be recalled that the placement of the capacitors 42 couplingthe word lines and the sense lines is arbitrarily preselected to providethe desired logic, and this is inverted according to the principles ofthe present invention as will be explained hereinafter. As a firstexample, consider the desire to provide an output on sense line S, foran input pulse on W, but no input pulse on any other word line. Theinput pulse on W, is inverted by inverter 30 and thereby provides a lowinput to AND gate 32. At clock time T,, the output of AND gate 32 is lowand line 38 has no signal thereon. The noninverted pulse on sense lineW, appears as a high signal on line 34 and thus provides an enablingsignal to AND gate 36. Upon the occurrence of the clock pulse T,, line40 carries a signal which, as seen by the capacitive coupling 42A,serves to activate or pulse sense line S,,.

Each input line W W, has its corresponding true line 50, 52 andcomplement line 54, 56 in the first plane. The absence of a pulse oninput lines W, through W causes an output pulse on each respectivecomplement line 54, 56 but no output on the true lines 50, 52. Line W,provides a pulse on complement line 54 which is also capacitivelycoupled 42B to sense line 8,. Input line W,,, by virtue of a pulse onits complement line 56 is capacitively coupled 42C to sense line 8,.Thus it may be seen that at clock time T, all the sense lines S, throughS, are pulsing but S, is not pulsing. This is part of the "invertedprocedure according to the principles of the present invention; allsense lines except the desired sense lines are pulsing.

Since the voltages on all pulsing sense lines exceed the thresholdvoltage V except any voltage which might appear on non-pulsing senseline 5, (which would indicate a low signal), the comparators 44 indicatethat each sense line exceeds its threshold voltage except for sense line5,. However, the inversion of comparators 44 provide an output which ishigh for sense line S, but low for all other sense lines, Thus there isa high signal to the D flip flop 46 associated with sense line S, and alow signal to all other flip flops. The output of each flip flop istaken from each 0 terminal 48.

The logical operation of a D flip flop will now be briefly summarized.Information present at the D or data input terminal is transferred tothe Q or output terminal when the clock pulse at the C input is high. Aslong as the clock pulse remains high, the Q output will follow the datainput. When the clock pulse goes low, the information that was presentat the data input D at the time of the clock pulse transition isretained at the 0 output until the clock pulse goes high again.

Returning to the operation of the logic portion of the circuit, justprior to and during the occurrence of a clock pulse T the output ofcomparator 44 associated with sense line S, was high (because of theinversion since S, was not pulsing) and the output of all othercomparators was low. Thus, during clock pulse T and at its conclusion,the D input of flip flop 46 on line S, is high but the D inputs andconsequently the Q outputs of the other flip flops are low. Thus it maybe seen from the logic of the present capacitive read only memory thatthe plurality of inversions provides an output from the flip flopassociated with sense line S, the combination of an input on line W, butno other input.

A second logic condition which will be explained is an input on lines W,and W,,. The occurrence ofa pulse on line W, appears as a pulse on itstrue line 40 at clock time T, and thus sense line S, will pulse. Theabsence of a pulse on input line W through its inversion provides anoutput pulse on complement line 54 and also pulsing sense line 5,. Thepulse on line W, results in an output pulse on true line 52 and senseline S, pulses. Since all sense lines are pulsing except sense line 8,,only the output 48 from the D flip flop 46 on sense line S, provides anoutput pulse at clock time T in the manner just described. 5

One third logic condition frequently utilized is the dont carecondition. That is, the logic on a particular line is immaterial. Forexample, suppose it is desired to indicate the absence of a pulse online W, and the presence of a pulse on line W whether or not a pulseoccurs on line W,,. Then the absence of a pulse on line W, results in apulse at time T, on line 38 thereby activating sense line 8,. Thepresence of a pulse on line W results in a pulse on true line 50 thuspulsing sense lines S, and 5,. Since it is immaterial whether or not apulse appears on line W,,, it is immaterial whether there is a pulse onits lines 52 or 56. In this situation, sense lines 8, and S, pulse butsense line S, is not pulsing which will result in a pulse through flipflop 46 on sense line 8,.

The operation of the CROM according to the principles of the presentinvention may thus be summarized as follows. Each input signal drivesthe capacitive matrix in both true and complement form. By the use ofinverters and by preselected capacitive coupling all sense lines exceptthe desired sense line are pulsed in response to the particular inputsignals. Output inverter logic responsive to the pulsing or non-pulsingcondition of the sense line provides an output signal only for thosesense lines which are not pulsing. Thus there is double inversion," thefirst to select the sense lines and the second to select the output flipflop.

Now that the operation of the AND or product CROM has been described,its utility by cascading it with other logical memories or matrices willnow be explained. With reference to FIG. 4, there is illustrated acapacitive OR matrix similar to that of FIG. 2 except that the OR matrixof FIG. 4 includes output circuitry. For illustration purposes, thematrix of FIG. 4 includes the flip flops 46 which are actually from thematrix of FIG. 3. The output 48 of each D flip flop 46 serves as oneinput to a two input AND gate 58, the other input being a clock pulse attime T The output of each AND gate 58 is one of the sense lines S,through 8,, respectively for the OR matrix of FIG. 4. The word lines ofthe matrix of FIG. 4 are identified as W, through W, with the capacitivecoupling 60 preselectedly based on the logic conditions desired.

Each word line serves as one input to a two input AND gate 62, theoutput of which serves as the data or D input to a D type flip flop 64.The outputs 0, through O, of the D type flip flops 64 are taken from theQ terminals. The other input to each AND gate 62 is a threshold voltageV The clock input or clock pulse to each flip flop 64 occurs at time TThe operation of the cascaded CROMs of FIGS. 3 and 4 will now beexplained. Only the logic identified with the first and second exampleof the explanation of FIG. 3 will be illustrated herein, since that willbe sufficient for the understanding of the principles of this invention.It may be recalled that the AND CROM of FIG. 3, in response to an inputpulse only on input line W, created an output pulse only from the flipflop 46 associated with sense line S,. If it is desired to provide anoutput pulse on all output word lines 0, through 0,, when sense line S,of FIG. 4 is activated, then capacitors 60 should be coupled to theintersection of sense line S and each word line W, through W, in theCROM of FIG. 4. Then, the presence of a pulse from the output of flipflop 46 associated with the sense line S, of FIG. 3 will be gated, attime T to sense line S, in the CROM of FIG. 4. The capacitive couplingwill activate all the word lines W, through W,. in the CROM of FIG. 4and, since these all will exceed the threshold voltage, all the gates 62will be enabled thereby providing data at the D input to each flip flop64. When the clock pulse T, goes low, the output on the Q terminal ofeach flip flop 64 will retain the signal which appeared at the time theclock pulse changed. Thus each output 0, through O, will provide anoutput signal.

The second condition explained with reference to FIG. 3 was thecondition of an input pulse on line W, and W,,. It will be recalled thatthis resulted in an output signal only from flip flop 46 associated withsense line 5,. If it is desired to provide outputs on lines 0, and 0,,of FIG. 4 when the flip flop 46 associated with the sense line 8, ofFIG. 3 is pulsing, capacitive coupling 60 between sense line S, and bothW, and W will be needed to provide such an output. Then, in the mannerjust described, both W, and W,, will be pulsed above the thresholdvoltage V AND gates 62 associated with W, and W will be enabled, andflip flops 64 associated with W, and W,, will provide output pulses.

Thus there has been shown and described a capacitive read only memoryoperable in the logical product mode by the inversion of the inputsignal and the inversion of the output signal. It has also been shownthat the output of the product matrix can be cascaded as the input ofanother matrix. While an OR matrix has been shown in FIG. 4, it must beappreciated that the various sense lines of FIG. 3 can serve as thesense lines of any logical matrix as desired. Furthermore the specificcircuitry for performing the two inversions may be varied withoutdeparting from the spirit and scope of my invention. Such variations arewell known to those skilled in the art. Depending upon the type ofinversion circuitry utilized of course, different types of output flipflops having different timing and logic characteristics may be utilized.An important aspect of my invention is in the strobing or pulsing of allsense lines except the desired sense line and this may only be performedby the use of a logical inversion prior to the input to the capacitivecoupling and a subsequent inversion at the output of the sense lines toprovide the desired output.

I claim:

1. In a capacitive read only memory including a matrix having aplurality of word paths and sense paths selectively capacitively coupledtogether, the improvement of circuit means for inverted operation ofsaid capacitive read only memory for providing the logical product ofinput signals comprising:

input means electrically coupled to said word paths and dividing eachsuch path into a true and a complement signal line,

means for delivering input pulses to the true signal lines and invertingsuch input pulses on said complement signal lines,

a double input terminal AND gate in each true and complement signal lineand receiving each input pulse on one of its two input terminals,

means for pulsing all of the sense paths except a desired sense path,said pulsing means including means for applying a strobe pulse for eachinput pulse to the other of said input terminals of said AND gates forenabling the same, and

output means for logically inverting the signals on all sense paths andthereby providing an output signal on said desired sense path forindicating the logical product of said input pulses.

2. In a capacitive read only memory according to claim I wherein eachsaid sense path has a register for storing an output signal conveyed byits respective sense path, each such register being normally in a firstlogical state but being responsive to an output signal on its respectivesense path for switching to a second logical state.

3. In a capacitive read only memory according to claim 2 wherein eachsuch register has a second logical state output and wherein a secondmatrix of electrically coupled word paths and sense paths has its wordpaths respectively electrically connected to the second logical stateoutputs of said registers.

4. A capacitive read only memory comprising:

a matrix having a plurality of sense lines selectively capacitivelycoupled to predetermined word lines wherein an enabling signal on one ofsaid word lines is coupled to selected ones of said sense lines,

logic means electrically coupled to said word lines of said matrix anddividing said word lines into a plurality of sets each having two lineswhere one line of each of said sets is electrically connected throughinversion means to said other line whereby the electrical signal on saidone line is a complement of the electrical signal on said other line,

a plurality of buffer registers operatively and electrically coupledrespectively to each one of said sense lines of said matrix, saidregisters being normally in a first logical state and responsive to asignal on its respective sense line for switching its associated bufferregister from said first state to a second logical state,

means for applying an electrical strobe pulse to all of said sense linesexcept those sense lines receiving an enabling signal from one of saidword lines, and

means for logically inverting the signals on said sense lines with theresult that only those buffer registers associated with the sense lineswhich bear signals after said inversion takes place are switched to saidsecond logical state.

5. A composable read only memory comprising:

a first matrix having a plurality of sense lines selectivelycapacitively coupled to predetermined word lines wherein an enablingsignal on one of said word lines is coupled to selected ones of saidsense lines,

a plurality of buffer registers operatively and electrically coupledrespectively to each one of said sense lines, said registers normally inone logical state and responsive to a signal from said first matrix forswitching said buffer register from said normal state to a switchedlogical state,

a second matrix having a plurality of word lines each electricallycoupled to the switched logical state output of each of said bufferregisters wherein an enabling signal from said switched logical state ofsaid bufi'er registers is coupled to selected ones of said word lines ofsaid second matrix,

logic means electrically coupled to said word lines of said first matrixfor dividing said word lines into a plurality of sets wherein anelectrical signal applied to said logic means for one of said sets willenergize only one word line in said set for enabling said first matrixand will deenergize all other word lines of said set, and

whereby said first matrix is a product generator performing a logicalAND function 6. A composable read only memory according to claim 5additionally including a plurality of buffer registers operatively andelectrically coupled respectively to each of said sense lines of saidsecond matrix said registers normally in one logical state andresponsive to a signal outputted from said second matrix on said senselines for switching said buffer from said normal state to a switchlogical state.

7. A composable read only memory according to claim 5 wherein said logicmeans divides said word lines into a plurality of sets having two lineseach where one line of each of said sets is electrically connectedthrough an inversion means to said other line whereby the electricalsignal on said one line is a complement of the electrical signal on saidother line.

k I. l i

1. In a capacitive read only memory including a matrix having aplurality of word paths and sense paths selectively capacitively coupledtogether, the improvement of circuit means for inverted operation ofsaid capacitive read only memory for providing the logical product ofinput signals comprising: input means electrically coupled to said wordpaths and dividing each such path into a true and a complement signalline, means for delivering input pulses to the true signal lines andinverting such input pulses on said complement signal lines, a doubleinput terminal AND gate in each true and complement signal line andreceiving each input pulse on one of its two input terminals, means forpulsing all of the sense paths except a desired sense path, said pulsingmeans including means for applying a strobe pulse for each input pulseto the other of said input terminals of said AND gates for enabling thesame, and output means for logically inverting the signals on all sensepaths and thereby providing an output signal on said desired sense pathfor indicating the logical product of said input pulses.
 2. In acapacitive read only memory according to claim 1 wherein each said sensepath has a register for storing an output signal conveyed by itsrespective sense path, each such register being normally in a firstlogical state but being responsive to an output signal on its respectivesense path for switching to a second logical state.
 3. In a capacitiveread only memory according to claim 2 wherein each such register has asecond logical state output and wherein a second matrix of electricallycoupled word paths and sense paths has its word paths respectivelyelectrically connected to the second logical state outputs of saidregisters.
 4. A capacitive read only memory comprising: a matrix havinga plurality of sense lines selectively capacitively coupled topredetermined word lines wherein an enabling signal on one of said wordlines is coupled to selected ones of said sense lines, logic meanselectrically coupled to said word lines of said matrix and dividing saidword lines into a plurality of sets each having two lines where one lineof each of said sets is electrically connected through inversion meansto said other line whereby the electrical signal on said one line is acomplement of the electrical signal on said other line, a plurality ofbuffer registers operatively and electrically coupled respectively toeach one of said sense lines of said matrix, said registers beingnormally in a first logical state and responsive to a signal on itsrespective sense line for switching its associated buffer register fromsaid first state to a second logical state, means for applying anelectrical strobe pulse to all of said sense lines except those senselines receiving an enabling signal from one of said word lines, andmeans for logically inverting the signals on said sense lines with theresult that only those buffer registers associated with the sense lineswhich bear signals after said inversion takes place are switched to saidsecond logical state.
 5. A composable read only memory comprising: afirst matrix having a plurality of sense lines selectively capacitivelycoupled to predetermined word lines wherein an enabling signal on one ofsaid word lines is coupled to selected ones of said sense lines, aplurality of buffer registers operatively and electrically coupledrespectively to each one of said sense lines, said registers normally inone logical state and responsive to a signal from said first matrix forswitching said buffer register from said normal state to a switchedlogical state, a second matrix having a plurality of word lines eachelectrically coupled to the switched logical state output of each ofsaid buffer registers wherein an enabling signal from said switchedlogical state of said buffer registers is coupled to selected ones ofsaid word lines of said second matrix, logic means electrically coupledto said word lines of said first matrix for dividing said word linesinto a plurality of sets wherein an electrical signal applied to saidlogic means for one of said sets will energize only one word line insaid set for enabling said first matrix and will deenergize all otherword lines of said set, and whereby said first matrix is a productgenerator performing a logical AND function.
 6. A composable read onlymemory according to claim 5 additionally including a plurality of bufferregisters operatively and electrically coupled respectively to each ofsaid sense lines of said second matrix said registers normally in onelogical state and responsive to a signal outputted from said secondmatrix on said sense lines for switching said buffer from said normalstate to a switch logical state.
 7. A composable read only memoryaccording to claim 5 wherein said logic means divides said word linesinto a plurality of sets having two lines each where one line of each ofsaid sets is electrically connected through an inversion means to saidother line whereby the electrical signal on said one line is acomplement of the electrical signal on said other line.